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I am seeking services for a time sensitive Formal Verification job for an small ASIC / IC design block. The job inludes the following items:
1) verifying a RTL design in Verilog and VHDL against a Gatelevel netlist
2) verify synthesis netlist against post-layout netlist
I offer hourly pay and compensation for tool costs for Cadence Verplex / Conformal or Synopsys Formality or similar tools.
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