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You need to implement in VHDL a 2-wide, 16-bit processor core that performs speculative, out- of-order execution based on Tomasulos algorithm and uses a reorder buffer to maintain precise state for recovering from exceptions and branch mispredictions.
The main blocks of this processor core consist of the following components:
8 reservation stations
16-entry reorder buffer
Register file with 16 registers. Each register is 16 bits.
8-entry load queue
8-entry store queue
The load and store queues process 16-bit memory addresses and 16-bit data for load and store instructions. Together, they form the memory ordering buffer (MOB). A top-level block diagram of the MOB is shown in the Memory Ordering file attached below.
The store queue and the load queue can be implemented as circular buffers, each with a head pointer and a tail pointer. Loads and stores are assigned entries in the load and store queues, in program order, in the front-end of the superscalar pipeline....
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