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I have a circuit that works on a Kintex 7 FPGA that I need implemented on a 28nm FD-SOI wafer. The design will have as many cores as we can fit on a 1mm2 die. The chip will be packaged in an FPBGA configuration.
Once the chip is laid out, I will need detailed power consumption estimates of the design as well as estimated clock speed ranges.
Please ask any questions you have.
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