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The required design is to be done in verilog HDL language. the purpose is to implement a 128 inputs work conserving round robin arbiter based on PPC(parallel prefix computation). the arbiter main features are:
- 128 bit input vector, each bit representing a request for the arbiter
- 7 bit output coding the next selected request
- 1 bit input indicating the last selection has been consumed and the arbiter can switch to the next request. this signal can be asserted for multiple clocks resulting in a valid output each clock
- 1 bit output indicating the result is valid, so if no request was asserted at the input, this bit would be de-asserted.
- synchronous design with asynchronous negative edge reset
- the input vector may change every clock so the new result should appear every clock.
- wrap around, meaning that when the round robin reaches the end of the vector, it will return to bits at the beginning. specifically, if request 128 is selected and request 0 is set, the next cycle wou...
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