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All JobsFPGA

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Fixed Price: Less than $500   |  Posted: 5h, 22m ago  |  Ends: 29d, 18h  |   2 Proposals
We are looking to hire a firmware developer to assist us on a project to read data from a CCD array using a ARM Cortex M3 microcontroller. We already have a working prototype from other freelance developers/open source designs and for this fixed price project we just want someone who show competence in understanding the project and help us migrate the firmware from one demo board to another. This job post is just to identify right freelancers and test their skills before we start working on a hourly basis. Experience in hardware oriented / embedded firmware development - Excellent Programming Skills in C language. Some experience with GUI using java, python etc desired too. - Should have working experience with Atmel/Freescale/STMicro development tools - A major plus if you have previous work experience with CCD - previous experience on low cost demo boards from NXP and TI - Knowledge of ARM Cortex Controllers & Digital Hardware Circuits is desirable - Should have excellent de...
Category: Electrical       

j****t87
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| j****t87
|    United States
Fixed Price: $500 - $1,000   |  Posted: 11h, 28m ago  |  Ends: 14d, 12h  |   3 Proposals
ITALIANO: Ricerchiamo un ingegnere elettronico con esperienza nella programmazione FPGA e generica e nel campo di crittografia, per collaborare allo sviluppo di un miner per l'algoritmo script (litecoin, dogecoin). preferibilmente italiano ma non necessariamente. Il progetto prevede la realizzazione di un miner con un potenza congrua alle difficoltà di mining attuali, pensavamo ad un 400MHs/s o superiore: possiamo fornire: - esperienza decennale nella realizzazioni di master e pcb anche multuilayer e disponiamo di software avanzato per il disegno elettronico -abbiamo accesso illimitato e gratutito ad un infinità di componenti elettronici -realizzazione dei PCB e prototipi rapidissima e presso un nostro terzista di fiducia a basso costo -possibilità di reperire facilmente E RAPIDAMENTE I COMPONENTI NECESSARI RICHIEDIAMO UNA PERSONA SERIA E CON ESPERIENZA ED APPASSIONATA NEL CAMPO DELLE CRYPTOVALUTE, PER LO SVILUPPO DELLO SCHEMA ELETTRICO E PER L'EVENTUALE PROGRAMMAZIONE. DISPONIBI...
Category: Electrical       

p****964
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| p****964
|    Italy
Fixed Price: $1,000 - $5,000   |  Posted: Jul 02, 2015  |  Ends: 4d, 18h  |   7 Proposals
We are looking for a talented FPGA programmer to help us implement a low noise (<10nV/(rootHz)) lock-in amplifier for heterodyne detection of sideband signals. Carrier frequencies range from 0.3 to 1.5MHz. The lock-in amplifier must have the ability to generate signals at specified frequencies and demodulate signals at the sum or difference of two frequencies (FM/heterodyne detection). Your job will be to develop a working prototype that does the following: 1) Takes in signals via a high speed, 16bit ADC 2) Generates a sine wave with programmable amplitude (ranging from 0 to 5V) and frequency, f2 = (1 to 1000Hz) 3) Demodulates the signals at two frequencies f1+f2, f1+2f2. f1 is determined from the DAC input. f2 is the frequency generated in step #2. 4) Outputs the RMS amplitude of the two demodulated signals via a low noise, 16bit DAC. We have an ADC and FPGA eval board already chosen, part #'s AD9268 and HSC-ADC-EVALCZ from Analog. You will need to help us choose the DAC and fi...
Category: Electrical       

N****lIR
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| N****lIR
|    United States
Hourly Rate: Less than $10 / hr   |  Duration: 1-2 weeks  |  Posted: Jul 01, 2015  |  Ends: 12d, 2h  |   2 Proposals
take charts/grafics information front stock charts , used the price values of bars H,L,O,C values into at x>y , if true=1 , if not =0 . also take values front indicatores in the chart/grafics and be able to aplicate same logic , result will be transfer to BINARY CALCULATOR , sample grafic used 6 variable fpga calculator has to be able to aplicate x>y=? and plot result into at excel page and . others detail will be sumit later
Category: Data Analysis       
Skills: Microsoft Excel, Excel VBA       

f****dia
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| f****dia
|    United States
Fixed Price: Not Sure   |  Posted: Jun 28, 2015  |  Ends: 8d, 11h  |   0 Proposals
High speed telecom signal interface standard SFI4.1 to be converted to XAUI interface. We have a SOC which gives SFI 4.1 16 lanes telecom signal(example STM64) which needs to be converted to XAUI or Interlaken to be decoded to get back the signal. Contraints: The SFI signals (32lines) to be connected via connector with 8 lines only(ex XAUI interface)
Category: Other IT & Programming       
Skills: MySQL Administration, HTML, PHP       

N****ata
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| N****ata
|    India
Fixed Price: Not Sure   |  Posted: Jun 25, 2015  |  Ends: 5d, 16h  |   7 Proposals
This is phase 1 of the project. Writing VHDL code to convert 12 K hz to 40 K hz HS video signals to standard VGA video signals using a FPGA and external RAM for screen display. Input signals will be digitized for the FPGA from a Analog AD9880-KSTZ-150, On screen display ( OSD)and input processed by a STC12LE5624AD micro controller. Input signals to be converted are STYLE (RGB(A), RGB(D), SOG, YUV, RGBS, RGBHV and YPbPr). OSD control will have Horz. position, width, Vert. position, height, phase, sync ( separate HV, composite HV, SOG and YUV. Resistance setting (75 ohm, 750 ohm) Scanning (progressive, interlaced).Screen resolution ( 640 X 480 and 800X600). Also in the OSD window it will show in real time the VS and HS input frequency. THE OSD function will display on default when no signal is present and have a time out to close when not being used. We will supply a prototype board for testing the VHDL code via a JTAG interface. And will provide a schematic of the prototype.(ID: 74...
Category: Other - Engineering &...       
Skills: Verilog / VHDL       

r****103
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| r****103
|    United States
Fixed Price: Less than $500   |  Posted: Jun 17, 2015  |  Ends: 12d, 19h  |   9 Proposals
Need to design a high speed counting circuit to detect the time difference between two separate signal pulses with 1nsec resolution. The leading edge of signal 1 pulse should start the count cycle, and the leading edge of signal 2 pulse should terminate the count cycle. Please advise on most appropriate design. I have been envisioning synchronous counters clocked at 1 Ghz with a total of 32 bits, which could pass data through shift register(s) for transfer of data to unknown interface (possibly FPGA). Counting cycle could be enabled with signal from a latching comparator, and disabled by the signal of an additional comparator. Once the count is collected, the cycle is reset for the next set of pulses. I have data sheets of circuit components that may work but am uncertain if they are the most appropriate selections. Deliverable includes selection and refinement of circuit components with associated BOM, generated circuit schematics, and associated PCB layout files. Phase 1 - Select...
Category: Electrical       

b****986
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| b****986
|    United States
Fixed Price: Not Sure   |  Posted: Jun 11, 2015  |  Ends: 66d, 6h  |   3 Proposals
I have an FPGA, and I need to 1. Program it to read Voltage, Current, Real Power, Reactive power, Power factor, Frequency, the first 50 orders of harmonics, and THD 2. Implement 3 communications protocols in it - Modbus, DNP3 and IEC61850 3. please indicate related work experiences and you rule in the job.
Category: Other IT & Programming       

a****ila
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| a****ila
|    United States
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