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All Jobsfpga

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Fixed Price: Not Sure   |  Posted: Jun 28, 2015  |  Ends: 11d, 11h  |   0 Proposals
High speed telecom signal interface standard SFI4.1 to be converted to XAUI interface. We have a SOC which gives SFI 4.1 16 lanes telecom signal(example STM64) which needs to be converted to XAUI or Interlaken to be decoded to get back the signal. Contraints: The SFI signals (32lines) to be connected via connector with 8 lines only(ex XAUI interface)
Category: Other IT & Programming       
Skills: MySQL Administration, HTML, PHP       

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| N****ata
|    India
Fixed Price: Not Sure   |  Posted: Jun 25, 2015  |  Ends: 8d, 17h  |   7 Proposals
This is phase 1 of the project. Writing VHDL code to convert 12 K hz to 40 K hz HS video signals to standard VGA video signals using a FPGA and external RAM for screen display. Input signals will be digitized for the FPGA from a Analog AD9880-KSTZ-150, On screen display ( OSD)and input processed by a STC12LE5624AD micro controller. Input signals to be converted are STYLE (RGB(A), RGB(D), SOG, YUV, RGBS, RGBHV and YPbPr). OSD control will have Horz. position, width, Vert. position, height, phase, sync ( separate HV, composite HV, SOG and YUV. Resistance setting (75 ohm, 750 ohm) Scanning (progressive, interlaced).Screen resolution ( 640 X 480 and 800X600). Also in the OSD window it will show in real time the VS and HS input frequency. THE OSD function will display on default when no signal is present and have a time out to close when not being used. We will supply a prototype board for testing the VHDL code via a JTAG interface. And will provide a schematic of the prototype.(ID: 74...
Category: Other - Engineering &...       
Skills: Verilog / VHDL       

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| r****103
|    United States
Hourly Rate: Not Sure   |  Duration: Not Sure  |  Posted: Jun 19, 2015  |  Ends: 2d, 22h  |   6 Proposals
We are developing a system which uses CPU / FPGA boards from RTD which are connected by PCI Express. The CPU will run Windows 7. the FPGA is a Spartan-6 from Xilinx. We need a windows driver / API to control the link.
Category: Software Application       

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| D****ch1
|    United States
Fixed Price: Less than $500   |  Posted: Jun 17, 2015  |  Ends: 15d, 20h  |   8 Proposals
Need to design a high speed counting circuit to detect the time difference between two separate signal pulses with 1nsec resolution. The leading edge of signal 1 pulse should start the count cycle, and the leading edge of signal 2 pulse should terminate the count cycle. Please advise on most appropriate design. I have been envisioning synchronous counters clocked at 1 Ghz with a total of 32 bits, which could pass data through shift register(s) for transfer of data to unknown interface (possibly FPGA). Counting cycle could be enabled with signal from a latching comparator, and disabled by the signal of an additional comparator. Once the count is collected, the cycle is reset for the next set of pulses. I have data sheets of circuit components that may work but am uncertain if they are the most appropriate selections. Deliverable includes selection and refinement of circuit components with associated BOM, generated circuit schematics, and associated PCB layout files. Phase 1 - Select...
Category: Electrical       

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| b****986
|    United States
Fixed Price: Not Sure   |  Posted: Jun 11, 2015  |  Ends: 69d, 7h  |   3 Proposals
I have an FPGA, and I need to 1. Program it to read Voltage, Current, Real Power, Reactive power, Power factor, Frequency, the first 50 orders of harmonics, and THD 2. Implement 3 communications protocols in it - Modbus, DNP3 and IEC61850 3. please indicate related work experiences and you rule in the job.
Category: Other IT & Programming       

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| a****ila
|    United States
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