• Over 17 years of association with semiconductor industry, focusing on chip design & development. Part of many successful chip designs such as solid state storage disk (Soc Processor) for SandForce. Part of the team that developed the Video architecture for Quartics video processor and main RAID engine for the Intel I/O processor. Multiple Intel PCI transparent chip designs (21152, 21154). Have semiconductor FAB experience.
Read More »
Architect and lead the team to develop the SSD controller IP and SSD model for algorithm analysis and firmware development.
Focusing on Big Data applications using the SSD, to see the particular feature implementation at disk level to reduce overall network traffic and power reduction through reducing data traffic on the network. This is done through scalable architecture using multiple flash controller each utilizing multiple channels to provide high bandwidth and reduce latency.
Apr 3, 2014|Electrical|Private|Completed
Dec 31, 2013|Electrical|Private|Completed
Dec 20, 2010|Electrical|Private|Completed
• Architected and managed the DDR3/4 development for 28nm node. Validated in FPGA environment.
• Managed the development of the Hybrid Memory Cube (HMC) controller.
• Architected the complete SSD controller architecture. Drove the development of the SSD controller modeling effort on architecture level.
• Architected and managed the different building blocks for SSD controller chip such as programmable Flash Controller for ONFI 3.0, high speed 8051 micro-controller and others.
• Managed the development of the ‘C’ based ONFI Flash Model in UVM environment.
• Managed the development activities for LDPC algorithm in MATLAB using signal processing techniques.
• Managed the training of multiple resources in UVM/SystemVerilog verification environment
• Guided software team for the development of the SSD controller models/algorithm.
• Managed the PCB level activities for required projects.
• Developed the 16-bit micro-controller that is compliant with Intel MCS 251 instruction set and Keil compiler. The Dhrystone v2.1 benchmark score is 0.258 DMIPS/MHz.
• Architected and oversaw USB 3.0 Host development that included Host Model, xHCI complaint layer, Data Link layer, Device Model, CPU bridges, hardware emulations, and device drivers.
• Development of storage architecture that includes on-chip based hardware file system such as Recycler, Read Disturb, Bad Block Management, Address Management, LZ based loss-less compression engine, security engine, Data Handler, Interrupt...
Read More »
Senior Member of Technical Staff
2004 - 2005
Video Processor (SOC) chip design & development. Assignments and activities include architecture & micro-architecture specification (MAS), RTL coding (using Verilog), logic synthesis and design...
Arizona State University
Technical Support Speicalist
1991 - 1995
Answered system-related questions. Performed tape backup, restore, and verification for all mainframe computers in ECS. Trained to perform emergency shutdown and re-boot of all mainframe computers....