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vaibhav rastogi | Elance
 
176985602337900
Last Sign-in: Sep 24, 2014

vaibhav rastogi

   India
  |   Meerut, Uttar Pradesh

Overview

I am B.E (Hons.) EEE from Bits Pilani Goa Campus. I am working in Xilinx as a software/IP developer for the past 1.5 years.
I take electronics as a puzzle and my objective is to fit in all the pieces of the puzzle and be a solution provider to engineering problems.

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Skills (10)

Tested
C++
Verilog
Perl
FPGA
Embedded Systems
Debugging
RTL design
Electronics Hardware Design

Employment

Xilinx
Software Engineer - I
2011 - Present
Working on EDK design suite used to design embedded designs for FPGA.
ST Microelectronics
Intern
2010 - 2010
Intern at Computer and Communication Infrastructure(CCI) depp. at St Microelectronics , Gr Noida My project involved RTL & Gate Level Verification,writing test bench for various IPs and...
NTPC
Intern
2009 - 2009
Intern at Control and Instrumentation Lab - Gas Plant at NTPC, Dadri. The project involved detailed study of various test bench equipments present at C&I lab and preparing a feedback report...

Education

Birla Institute of Technology and Science
B.E Hons.
-
Dayawati Modi Academy - I
Inter
-
Overview  |  Job History  |  Resume/C.V.

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Identity
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curiousguy
Type
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Member Since
September 2014
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vaibhav rastogi | Elance

vaibhav rastogi