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Evangelia D. | Elance
 
176985602337900
Last Sign-in: Dec 9, 2012

Evangelia D.

FPGA/ASIC Design Engineer
   Greece
  |   Agia Paraskevi, Attica
  |  6:59 pm Local Time

Overview

Minimum Hourly Rate $20

Thank you for viewing my profile. I am mainly specialized in VHDL implementation of DSP algorithms. Well aware of FPGA technologies (Xilinx, Altera), able to provide excellent area and timing results. Also, experienced in ASIC flows, STA (PrimeTime), BIST. Expert in tcl/tk scripting. Clean, portable VHDL code following RMM rules.

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Skills (3)

Tested
Digital Electronics
Integrated Circuits
VLSI

Employment

Intracom Telecom
Digital Design Engineer
1996 - Present

Education

University of Manchester (UMIST), United Kingdom
M.Sc. in VLSI Systems Engineering
1994 - 1995
University of Patras, Greece
Electrical Engineering and Computer Technology
1989 - 1994

Keywords

My Snapshot
Elance Level
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  • 12 months
  • Lifetime
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Identity
Username
evadiama
Type
Individual
Member Since
November 2012
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Evangelia D. | Elance

Evangelia D.