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Gerard S. | Elance
 
176985602337900
Last Sign-in: Feb 25, 2015

Gerard S.

Software Engineer
   United States
  |   Baltimore, MD

Overview

Digital Design Engineer with over three years of FPGA & CPLD design work.
Experience with Altera, Xilinx, and Modelsim

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Skills (8)

Tested
C++
C
Java
TCP/IP
Red Hat Administration
Internet Security
Internet Security
My Score
avg
Networking & Security
Networking
My Score
avg
Network Administration
Computer Networking
My Score
avg
Passed

Service Description

I can work with you to help formulate your design architecture. I will work out multiple level block diagrams. Design each functional block in the system. Test each functional block, then test the entire system to ensure the end result met your design need and requirements.

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Employment

NG
Cyber Software Engineer
2012 - Present
- Developing applications on tile architecture processor in C++
ITT Corporation
Technical Intern
2011 - 2011
- Used VHDL to design Digital Hardware for a CPLD under tight low power constraints. - Used Altium Designer to design the schematic layout for a test adapter board.
Intel Corporation
Signal Integrity Intern
2009 - 2010
- Validated high speed differential signals leaving Intel silicon or package (SATA 2, PCIe 2 ect.). - Developed a new test methodology for Stellarton product. - Used Python to...

Education

Howard University
Bachelor of Science in Electrical Engineering
2006 - 2012

Keywords

Digital Design
VHDL
PCB Design
Embedded Design
Microcontoller
My Snapshot
2
Elance Level
Level represents activity and experience on Elance. Freelancers start at Level 1 and achieve higher levels through their work. A higher "Level" indicates greater earnings, ratings and other achievements on Elance. Learn More »
  • 12 months
  • Lifetime
Jobs
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0
Total
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Clients
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Identity
Username
gerdanspy
Type
Individual
Member Since
January 2012
Elance URL
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Gerard S. | Elance

Gerard S.