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Kiran Yalamanchi | Elance
 
176985602337900
Last Sign-in: Feb 15, 2012

Kiran Yalamanchi

ASIC/FPGA Design and Verification Engineer
   United States
  |   Chicago, IL

Overview

Minimum Hourly Rate $27

Interested in:
Low Power ASIC Design
Implementation of DSP algorithms for FPGA synthesis
Computer Architecture
RTL level implementation in Verilog and VHDL
VMM for verification

Read More »

Skills (10)

Tested
VLSI
Circuit Design
Digital Signal Processing
Knowledge of Microsoft Office
OOPS
Linux
Unix
C
C++
Perl

Education

Illinois Institue of Technology
Master of Science in Electrical Engineering
2010 - 2011

Keywords

My Snapshot
Elance Level
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  • 12 months
  • Lifetime
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Identity
Username
kyalama2
Type
Individual
Member Since
February 2012
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Kiran Yalamanchi | Elance

Kiran Yalamanchi