Muhammad Akhtar | Elance
 
176985602337900
Last Sign-in: Aug 31, 2015

Muhammad Akhtar

ASIC / FPGA Design / Verification professional
   Pakistan
  |   Islamabad, Ict
  |  8:47 pm Local Time

Resume/C.V.

Eight Years Experience in Semiconductor Industry

Specialties

ASIC / FPGA Front End Design, Verification
FPGA Design for DSP

SystemVerilog, VERILOG and VHDL,

Synopsys Design Compiler, IC Compiler, VCS.

Xilinx ISE , Vivado, Xilinx Chipscope Pro.

Cadence Virtuoso, NC-Verilog, Simvision, SoC Encounter

Mentor Graphics ModelSim 10, Questa Sim, Calibre Design REV, DRC, LVS, PEX.

Service Description
ASIC Verification using UVM / VMM
ASIC / FPGA RTL Design

Digital ASIC Design, FPGA Design,
ASIC Synthesis / STA using Synopsys / Cadence tools.

RTL Design, Synthesis, Place and Router, Logic and Timing Simulation in VERILOG and VHDL for Xilinx FPGAs

PCB Design for FPGAs using Orcad / Altium.
I have access to latest EDA tools for Synopsys / Cadence i.e. Synopsys Design Compiler / IC Compiler / VCS-MS / Leda / Synplify Premier / Cadence Incisive / Soc Encounter / Xilinx ISE / Vivado / Modelsim / Questasim.
Education
Portland State University
MS ECE
2007 - 2009
Employment
Open Silicon
Principal Design Engineer
2012 - 2013
ASIC Synhesis (Synopsys Design Compiler) ASIC DFT (Synopsys Design Compiler) ASIC STA (Synopsys Design Compiler) ASIC Varification (Synopsys VCS + UVM)
Payment Terms
None specified
Muhammad Akhtar | Elance

Muhammad Akhtar