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Peter K. | Elance
 
176985602337900
Last Sign-in: Feb 23, 2015

Peter K.

+7 years of experiance in VHLD/Verilog/matlab/C.
   Slovenia
  |   Ljubljana, Ljubljana
  |  5:26 pm Local Time

Overview

Minimum Hourly Rate $27

I have +7 years of experience in VLSI development (VHDL/Verilog fpga/asic), in firmware development C, algorithm development (matlab) and in Linux scripting (bash, python).

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Skills (10)

Tested
Linux System Administration
Linux Test
My Score
avg
Passed
verilog
C
Python
VLSI
MATLAB
Bash
Field-Programmable Gate Array (FPGA)
ASIC
Image Processing

Employment

Aptina Imaging
ASIC Developer
2009 - 2015
Worked on state of the art imaging algorithms and SOC chips. - Developed module level and top level RTL - Verified complete designs - Developed architecture for SOC chips. - Developed firmware
inSilica Inc.
ASIC developer
2006 - 2009
- developed multiple verilog modules - tested multiple verilog modules - tested top level soc design

Education

University of Ljubljana
Bachelor of Computer Science
-

Keywords

VHDL verilog fpga asic verification linux bash python c matlab
My Snapshot
IT & Programming
1
Elance Level
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  • 12 months
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Identity
Username
musli
Type
Individual
Member Since
November 2012
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Peter K. | Elance

Peter K.