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Pietro Centoletti | Elance
 
176985602337900
Last Sign-in: Jul 4, 2013

Pietro Centoletti

FPGA, ASIC & HW designer , System Architect
   Italy
  |   L' Aquila, Italy

Overview

I am a senior FPGA, ASIC & HW designer with in depth knowledge of Verilog and VHDL languages. I am involved in
HW design of router and gateway systems. All routers run Linux operating system and implement all known routing protocols (RIP I&II, OSPF, BGP). The interfaces are ISDN BRI & PRI, ADSL, ADSL2/2, VDSL2, Ethernet, GSM/GPRS/EDGE/UMTS/HDPA, serial, WIFI

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Skills (4)

Tested
Electronic Design
Embedded Systems
VLSI
Fiber Optics

Service Description

Profile Type: Individual
My name is Pietro Centoletti and I live in Tuscany (Italy) and work in Tuscany and Abruzzo (Italy). I have been working with major companies in US and Europe. I have great experience with VHDL, Verilog and microprocessors like Intel XScale, AMCC PP40x, Atmel AT9x, Samsung S3Cx, Freescale iMX2x, iMX3x, PSOC and I can deliver turnkey solutions if needed.

Consultancy and design - I can join your team in order to respect the programmed development time, bringing design experience and advance methodologies.

Turn key design - I can take the responsability and leadership of the project - from concept to definition and implementation of parts - and provide the system

Telecommunication system - I provide my experience in the telecommunication field - broadband, narrowband and wireless - to accelerate the project of your system and to insure the compliance to the standards.

I am absolutely confident about the professional skills, experience and approach and I can insure that all will help you to have predictable and well defined results.

My services encompass the entire HW & ASIC/FPGA development lifecycle.

Concept development
Features definition
Requirements definition
Specifications definition
HW and/or ASIC/FPGA design
HW and/or ASIC/FPGA verification
HW and/or ASIC/FPGA test


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Employment

KASKO NETWORKS
SYSTEM ARCHITECT & HW/FPGA DESIGNER
2002 - 2008
System Architect / Hw & ASIC designer working on the definition of the architecture and on the implementation of routers and gateways
SIEMENS
SYSTEM ARCHITECT
1997 - 2001
I was working as system architect defining the architecture of SDH systems in particular for what concern the ASIC sed in that system
ITALTEL
ASIC DESIGNER
1991 - 1996
I worked as ASIC designer working in the position of project leader on line interface ASICs for SDH ADM & DXC for STM1/4/16 systems
ATT & ITALTEL
ASIC DESIGNER
1990 - 1991
During this period I was working in ATT Labs in Huizen - NL. My job position was ASIC designer working on SDH & DXC system. I implemented a Bus transceiver and Pointer processor fo STM1/4 systems
TEXAS INSTRUMENTS
FULL CUSTOM DEVICE DESIGNER
1988 - 1990
In this period I worked in the Sdram design group of Texas Instruments in Houston (TX)-USA. My job position was Full Custom analog circuit designer working on 4 Mbits and 16 Mbits Sdram device
ITALTEL
HW & FPGA DESIGNER
1986 - 1988
Hardware designer working on powerline comunication to remotely control power meter systems. I was involved in FPGA design of an all digital powerline modem.

Keywords

VHDL
Verilog
FPGA
Embedded System Design
System Architecture
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Identity
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pcentoletti
Type
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Member Since
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Pietro Centoletti | Elance

Pietro Centoletti