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Paraskevas Havos | Elance
 
176985602337900
Last Sign-in: Jul 28, 2014

Paraskevas Havos

FPGA/ASIC design engineer.
   Greece
  |   Alimos, Athens

Overview

Summary:
Expertise in FPGA/ASIC Design & Verification with emphasis on wireless telecommunications, & video systems.
Excellent debugging skills with standard EDA tools for simulation, synthesis and timing analysis.
Expertise in implementing algorithms written in ANSI C/matlab to functional RTL with vhdl.

Specialities:
1. Designing ASICs or FPGAs for mobile backhaul systems and for image video processing. Ability to write detailed design specifications.
2. Porting uclinux using microblaze soft core.
3. Digital Communications : Design and...

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Skills (9)

Tested
Digital Design
VLSI
Altera
ModelSim
DSP
ISE
quartus
Cadence
Digital Electronics

Service Description

FPGA/ASIC design engineer

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Employment

Intracom Telecom
Senior VLSI designer
2006 - Present
- Technical lead of several FPGA projects. - Responsible of implementation and verification of FPGAs that are used in point to point native ethernet back-haul wireless systems & for point to...
ISD S.A.
VLSI engineer
2002 - 2006
- FPGA technical lead of multi-board architecture project that can be utilized in order to capture, multiplex and deliver to PC main memory (through the PCI bus) in real time, video frames...

Education

University of Athens
Master of Science (MSc)
-
Univercity of Patras Science devision
Bachelor on Physics
-

Keywords

FPGA ASIC vhdl verilog Xilinx Altera
My Snapshot
IT & Programming
1
Elance Level
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Identity
Username
phavos
Type
Individual
Member Since
January 2013
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Paraskevas Havos | Elance

Paraskevas Havos