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R. Shawn H. | Elance
 
176985602337900
Last Sign-in: Dec 20, 2014

R. Shawn H.

EE look for contract work
   United States
  |   Sebastopol, CA
  |  2:34 am Local Time

Overview

Minimum Hourly Rate $55

Results-oriented Engineer with board expertise in Mixed-Signal Circuit Design. My involvement starts at specification, and generally continues past silicon evaluation. Strong Systems and Top-Level design skills have lead me to designing Integrated Circuits in a variety of application areas including Video, Audio, Imaging, and Communications. In all of these designs strong team building skills were critical in meeting schedule and product specifications.

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Skills (10)

Tested
CMOS circuit design
Mixed signal circuit design
Verilog
FPGA
Verification
ADC/DAC
DSP
Analog Signal Processing
Audio

Service Description

Experience:

Summer 2005-present
Senior Staff Mixed Signal Design Engineer
Responsible for System and Top-Level Design of analog and mixed-signal systems. I have been a technical and collaborative lead through all phases of the CMOS IC design process. The following include projects at:
HDMI/DVI Repeater - 2.2Gbits/s LVDS in 0.18um CMOS
Top-Level architecture, integration, and Circuit Design
Top-Level simulation and verification
Advised and lead analog and digital engineers to meet block level specification
Research and Outlined HDMI specification to designers
Video/Imaging Analog Front End - 170 MHz 10 bits in 0.18um CMOS
Flash ADC system design %u2013 performance optimizations
Top-Level Design and Verification
Digital Design %u2013 Dither, Encoder
ADC - Sigma Delta %u2013 12 bit resolution 12 oversampling 25 MHz bandwidth
System Modeling using Matlab,Verilog A, and Spice
Top Level assembly
Pipeline %u2013 14 bit 100 Mhz in 0.18u
Verification and simulation of top-level

Summer 2002 %u2013 Summer 2005
Staff Mixed Signal Design Engineer
Responsible for System and Top-Level Design of analog/mixed-signal system including:
Video/Imaging Analog Front End - 300 MHz 8 bits in 0.18um CMOS
Flash ADC system design %u2013 Timing and performance optimizations
Top-Level Design and Verification
Circuit Design %u2013 controls, timing circuits, ADC Encoders
Video/Imaging Analog Front End - 170 MHz 10 bits in 0.18um CMOS
Flash ADC system design %u2013...

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Overview  |  Job History  |  Resume/C.V.

Keywords

verilog
mixed-signal
simulation
modeling
electrical
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rshawnh
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Member Since
December 2010
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R. Shawn H. | Elance

R. Shawn H.