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Goa University | Elance
 
176985602337900
Last Sign-in: Apr 27, 2012

Goa University

Asic design engineer
   India
  |   Siolim, Goa

Overview

Mahesh Salgaonkar
I have one year experience as ASIC ENGINEER .I am a Post graduate student .I have masters degree in Electroics from Goa university and DIPLOMA IN VLSI from CDAC.
I have won a FIRST PLACE at the Mentor Graphics University Design contest 2010 in India.I have done a Uart verification using VHDL for CDAC project.
ALSO got Experience in Teaching hardware languages.

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Skills (1)

Tested
VLSI

Service Description

I am working in the field of vlsi.i have working knowledge of VHDL,verilog,System verlog and FPGA.I can provide my service in coding using above languages.verification of the module and testbench serice i can provide.

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Keywords

vlsi
asic
vhdl
verilog
system verilog
Company Snapshot
1
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Identity
Username
salgaonkar
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Member Since
March 2011
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Goa University | Elance

Goa University