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Satbinder R. | Elance
 
176985602337900
Last Sign-in: May 9, 2013

Satbinder R.

Sr. ASIC/FPGA Design & Verification Consultant
   Denmark
  |   Herlev, Copenhagen

Overview

I'm 37 years an independent HW consultant and have worked on FPGA and ASIC projects. I''ve worked in all phases of design and verification during my 11 years work experience.

I am an energetic, innovative, self-motivated and hard-working expert. I can take initiative and am a quick learner, with very little need for coaching. These talents, as well as my active participation and well-developed technical skills, make me a strong team player, cooperating well with others. With my positive and results-oriented attitude, I produce good...

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Skills (1)

Tested
VLSI

Service Description

I have been working with model/design and verification of products since summer 1999, during this period several products have been developed and sent to production, Further I'm expert not only developing hardware or software but I do put a lot of effort to verify what has been developed. During my work with ASIC design centers I'm expert in developing and verifying ASIC/FPGA blocks.

For the last 2 years I have been focusing on new verification methodologies like VMM, OVM and recently UVM and have developed test benches using those methodologies not only for ASIC but also FPGA block and system level designs.

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Employment

SyoSil, AXIS and Zeuxion
Verification Consultant
2009 - 2011
2009-2010 1st January 2009, consultant at SyoSil. The company works mainly with verification methodologies and helps their customers with incorporation of VMM or OVM methodology. The focus is to...
SwitchCore AB, Ericsson
Consultant
2006 - 2009
Worked on different RTL design projects: I became an independent consultant and established my own company. The first assignment was at Switchcore AB in Lund on a contract basis for 16 months...
Vitesse Semiconductor Denmark
ASIC Engineer
2000 - 2005
Joined Exbit Technology (Vitesse Semiconductor) as an ASIC-engineer. They design/verify and validate Switches/MACs ICs for the Ethernet LAN/MAN/WAN/SAN market. I began in the verification team and...
Barconet
Research and Design Engineer
1999 - 2000
August 1999. I worked at Barconet (Scientific Atlanta), developers of complete solutions for the telecom market. I was an R&D-Engineer for the MPEG-2 decoder group. I developed a complete...

Education

Engineering College of Copenhagen
Bachelor of Science in Electronics Engineering
1995 - 1999

Keywords

VHDL
SystemVerilog
OVM/VMM
Testbench
RTL
My Snapshot
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Identity
Username
satbinderram
Type
Individual
Member Since
January 2011
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Satbinder R. | Elance

Satbinder R.