Jul 16, 2013|$182|Software Application|Completed|
I am a novice to HDL and I put together a Verilog design using ISE 12.4 and a Xilinx cpld. It is about 100 lines long depending on how you look at it. The project synthesizes without errors but has a number of warnings. Most sound like they can be ignored but some don't. I would like for someone to fix the important warnings and then write some sim...
Skills: application programming
“This was my first time to use elance and it went well. Avinash had the right tools to work on the cpld and had the right skill set (working in Verilog) for doing the job. I would definitely recommend him.”
“Thank you Steven”