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Randy Y. | Elance
 
176985602337900
Last Sign-in: Apr 17, 2014

Randy Y.

25 years in system, hardware, and software design
   United States
  |   Fuquay Varina, NC
  |  5:17 pm Local Time

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Overview

Minimum Hourly Rate $49

Degreed electrical engineer and mathematician specializing in digital signal processing, real-time embedded systems, linux/windows development, database design, digital/analog hardware design, circuit board layout.

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Jan 27, 2014|Other IT & Programming|$50|Completed
|
4.9
Oct 23, 2013|Other IT & Programming|$0|Completed
Jan 21, 2013|Other IT & Programming|$6,000|Working
Jan 12, 2013|Other IT & Programming|$858|Working

View All »

Portfolio

An introduction to fixed-point arithmetic.
How to scale coefficients, account for guard bits in extended accumulators, etc.
A presentation at the first comp.dsp conference covering the basics of delta sigma D/A...
This paper describes a simple, efficient, and numerically superior algorithm for...
A short paper deriving the -1.6 dB limit on power efficiency in information theory.
An example of highly-optimized, SSE2 x86 code.
This is an example of highly-optimized TI TMS320C54x DSP code.
This is a tutorial I wrote for an Elance customer on coding theory.

Skills (9)

Tested
Digital Signal Processing
Digital Signal Processing Test
My Score
avg
Embedded Systems
Microsoft Access Administration
Microsoft Access 2003 Test
My Score
avg
Electronic Design
PCB Design
PostgreSQL Administration
AJAX
HTML
Data Modeling

Service Description

o Architected and implemented physical layer modules for the FSK mode of the 802.15.4g Smart Utility Network
(wireless network) on a Texas Instruments TMS320F28M35 Concerto microcontroller in oxed-point assembly
and C, using Matlab and Code Composer Studio 5.1, including:

~ Implementation of a R = 1/2, K = 4 Viterbi decoder in highly optimized assembly and VCU.

~ Implementation of the modulator, demodulator, decimator, resampler, interpolator, whitener, interleaver,
and Viterbi encoder in C and highly-optimized assembly.

~ Architected and prototyped CLA subsysystem software for the receive chain front-end processing on the
upcoming next-generation Concerto microcontroller.

* Architected memory movement, DMA, and SPI interfaces to the CLA subsystem.

* Architected AGC loop approach and algorithm.

* Prototyped gain control and decimator algorithms in highly optimized CLA assembly language.

o Participated in the evolution of next-generation Texas Instruments C28x microcontrollers and tools:

~ Evolved the Viterbi VCU instruction set by exposing a limitation in the constraint length of the current
VTRACE VCU instruction.

~ Assisted the compiler team in another level of optimization of their C compiler by providing an example
in which my hand-coded assembly out-performed their compiled code by a factor of 4.3x.

~...

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Education

North Carolina State University
graduate coursework in digital communication/digital signal processing
2003 - 2008
University of South Florida
Bachelor of Arts, Mathematics
1994 - 2001
University of South Florida
Bachelor of Science, Electrical Engineering
1993 - 1997
DeVry Institute of Technology
Bachelor Science Electronic Engineering Technology
1976 - 1979

Keywords

DSP
communications systems
signal processing
digital audio
PHY layer implementation.
My Snapshot
4
Elance Level
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  • 12 months
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Reviews
4.9
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Identity
Username
yatescr
Type
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Member Since
May 2008
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Randy Y. | Elance

Randy Y.